6th Workshop on Parallel Programming Models -- Special Edition on Fog and In-Situ Computing
MPP 2017
- URL: http://mpp2017.ime.uerj.br/
- Event Date: 2017-10-17 ~ 2017-10-20
- Submission Date: 2017-08-13
- Location: Campinas, Brazil
To be held in conjunction with the 29th International Symposium on
Computer Architecture and High Performance Computing (SBAC-PAD 2017)
Important Dates:
Paper submission deadline: August 13, 2017
Author notification: September 10, 2017
Camera ready: September 17, 2017
Writing parallel applications is an arduous and non-trivial task, but also mandatory if one wants to explore the potential of modern multicore processors. This task becomes even harder as different computation devices, such as General Purpose Graphic Processing Units (GPGPUs) and Field Programmable Gate Arrays (FPGAs), are employed to build heterogeneous systems. This imposes new challenges to the scientific community: the creation of models and alternatives to ease parallelism exploitation by the average programmer, considering the peculiarities of the different computation devices.
Another important aspect to consider, specially in applications that run on big systems and manipulate big datasets, is the tradeoff between moving data to a remote processing element to increase parallelism and computing things locally to reduce communication costs. Fog and in-situ computing intend to tackle this issue by adding computing capabilities to network devices (such as NICs, switches and routers), storage devices or even memory. Those "smart" devices would be able to perform part of the computation that would reduce data transmission over the network and data busses. This makes computing systems even more heterogeneous, intensifying the need of novel programming models.
MPP aims at bringing together researchers interested in presenting contributions to the evolution of existing models or in proposing novel ones, considering the trends on accelerator devices and fog/in-situ computing. MPP 2017 will be held in conjunction with the 29th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2017), at Campinas, São Paulo, Brazil.
MPP invites authors to submit unpublished full papers on the subject. Submissions must be in English, 6 pages maximum, following the IEEE formatting guidelines. The 6-page limit includes references. Topics of interest include (but are not limited to):
Data-Flow execution models and languages for parallelism exploitation;
Languages, compilers and parallelism extraction tools
Heterogeneous programming models
Synchronization Mechanisms, such as Transactional Memories
Load-balancing for multithreading
Scheduling and Placement Algorithms for Parallel Programming models
Novel Parallel Programming Techniques
Novel Parallel Architectures
Error Detection/Recovery for Parallel Programming Models
Theoretical Analysis of Parallelism.
Smart storage and in-situ computing
Fog computing
Program co-chairs
Leandro Augusto Justen Marzulo - UERJ, Brazil
Felipe M. G. França - UFRJ, Brazil
Cristiana Bentes - UERJ, Brazil
Vladimir Alves - NGD Systems, USA
Program Committee (under construction)
Alexandre da Costa Sena - UERJ, Brazil
Alexandre Solon Nery - UERJ, Brazil
Aline de Paula Nascimento - UFF, Brazil
Andrew Putnam - Microsoft, USA
Carla Osthoff - LNCC, Brazil
Diego Dutra - UFRJ, Brazil
Edson Borin - UNICAMP, Brazil
Elias Mizan - Synaptics, USA
Emilio Francesquini - UNICAMP, Brazil
Francisco Sant'Anna - UERJ, Brazil
Gabriel Paillard - UFC, Brazil
Hung Wei Tseng – North Carolina State University, USA
Igor Machado Coelho - UERJ, Brazil
Inês Dutra - Univ do Porto, Portugal
Lúcia Drummond - UFF, Brazil
Marcelo Zamith - UFRRJ, Brazil
Maria Clicia Stelling de Castro - UERJ, Brazil
Maurício Pilla - UFPEL, Brazil
Rafael Burlamaqui Amaral, CEFET-RJ, Brazil
Rafaelli Coutinho, CEFET-RJ, Brazil
Rekai Gonzalez Alberquilla - ARM, UK
Ricardo Farias - UFRJ, Brazil
Sandip Kundu - UMASS, USA
Tiago A. O. Alves – UERJ, Brazil
Ubiratam de Paula - UFRRJ, Brazil
Walid Najjar - University of California Riverside, USA
Zehra Sura - IBM, USA
Computer Architecture and High Performance Computing (SBAC-PAD 2017)
Important Dates:
Paper submission deadline: August 13, 2017
Author notification: September 10, 2017
Camera ready: September 17, 2017
Writing parallel applications is an arduous and non-trivial task, but also mandatory if one wants to explore the potential of modern multicore processors. This task becomes even harder as different computation devices, such as General Purpose Graphic Processing Units (GPGPUs) and Field Programmable Gate Arrays (FPGAs), are employed to build heterogeneous systems. This imposes new challenges to the scientific community: the creation of models and alternatives to ease parallelism exploitation by the average programmer, considering the peculiarities of the different computation devices.
Another important aspect to consider, specially in applications that run on big systems and manipulate big datasets, is the tradeoff between moving data to a remote processing element to increase parallelism and computing things locally to reduce communication costs. Fog and in-situ computing intend to tackle this issue by adding computing capabilities to network devices (such as NICs, switches and routers), storage devices or even memory. Those "smart" devices would be able to perform part of the computation that would reduce data transmission over the network and data busses. This makes computing systems even more heterogeneous, intensifying the need of novel programming models.
MPP aims at bringing together researchers interested in presenting contributions to the evolution of existing models or in proposing novel ones, considering the trends on accelerator devices and fog/in-situ computing. MPP 2017 will be held in conjunction with the 29th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2017), at Campinas, São Paulo, Brazil.
MPP invites authors to submit unpublished full papers on the subject. Submissions must be in English, 6 pages maximum, following the IEEE formatting guidelines. The 6-page limit includes references. Topics of interest include (but are not limited to):
Data-Flow execution models and languages for parallelism exploitation;
Languages, compilers and parallelism extraction tools
Heterogeneous programming models
Synchronization Mechanisms, such as Transactional Memories
Load-balancing for multithreading
Scheduling and Placement Algorithms for Parallel Programming models
Novel Parallel Programming Techniques
Novel Parallel Architectures
Error Detection/Recovery for Parallel Programming Models
Theoretical Analysis of Parallelism.
Smart storage and in-situ computing
Fog computing
Program co-chairs
Leandro Augusto Justen Marzulo - UERJ, Brazil
Felipe M. G. França - UFRJ, Brazil
Cristiana Bentes - UERJ, Brazil
Vladimir Alves - NGD Systems, USA
Program Committee (under construction)
Alexandre da Costa Sena - UERJ, Brazil
Alexandre Solon Nery - UERJ, Brazil
Aline de Paula Nascimento - UFF, Brazil
Andrew Putnam - Microsoft, USA
Carla Osthoff - LNCC, Brazil
Diego Dutra - UFRJ, Brazil
Edson Borin - UNICAMP, Brazil
Elias Mizan - Synaptics, USA
Emilio Francesquini - UNICAMP, Brazil
Francisco Sant'Anna - UERJ, Brazil
Gabriel Paillard - UFC, Brazil
Hung Wei Tseng – North Carolina State University, USA
Igor Machado Coelho - UERJ, Brazil
Inês Dutra - Univ do Porto, Portugal
Lúcia Drummond - UFF, Brazil
Marcelo Zamith - UFRRJ, Brazil
Maria Clicia Stelling de Castro - UERJ, Brazil
Maurício Pilla - UFPEL, Brazil
Rafael Burlamaqui Amaral, CEFET-RJ, Brazil
Rafaelli Coutinho, CEFET-RJ, Brazil
Rekai Gonzalez Alberquilla - ARM, UK
Ricardo Farias - UFRJ, Brazil
Sandip Kundu - UMASS, USA
Tiago A. O. Alves – UERJ, Brazil
Ubiratam de Paula - UFRRJ, Brazil
Walid Najjar - University of California Riverside, USA
Zehra Sura - IBM, USA
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