Parallel Computing with FPGAs
ParaFPGA 2017
- URL: http://parafpga.elis.ugent.be/
- Event Date: 2017-09-12 ~ 2017-09-15
- Submission Date: 2017-06-10
- Location: Bologna, Italy
ParaFPGA2017 is a mini-symposium organized in conjunction with the biennial Parallel Computing conference ParCo2017, to be held in Bologna, Italy on 12-15 September 2017.
SCOPE
Parallel computing with Field Programmable Gate Arrays (ParaFPGA) brings together research on tools, programming environments and applications using FPGAs for high performance computing. High performance computing requires new avenues and creative solutions to alleviate the power and frequency limitations of today's processors. Accelerators are becoming the mainstream approach for delegating compute intensive tasks to appropriate hardware. The diversity of architectures and high-level synthesis designs are harnessed with common languages such as OpenCL combined with dedicated programming and synthesis environments.
Researchers and practitioners are invited to submit original contributions on the methodology and use of parallel computing with FPGAs. Papers are solicited in areas including but not limited to:
- performance analysis of high-level synthesis
- design space exploration using HLS
- applications of parallel techniques with FPGAs e.g. in big data, deep learning, biology and finance
- high-level synthesis debugging
- domain specific synthesis languages
- optimizing memory locality and data paths
- partial reconfiguration and optimal ip-core (re)use
- managing a run-time library of ip-cores
- use of hybrid CPU/GPU/FPGA systems e.g. in real-time video or automotive systems
- modeling and simulation of FPGA architectures and applications
PAPERS
Authors are invited to submit a full paper of maximum 10 pages or an extended abstract of minimal 4 pages. The approved contributions will be presented at the conference and the accepted full papers are published in the ParCo proceedings.
Details regarding the format, presentation and paper submission are given on the author guidelines page.
Deadline for the submission is 10 June 2017
COMMITTEES
Steering committee:
Gerhard R. Joubert (Conference chair)
Sanzio Bassini (Organizing committee chair)
Frans Peters (Finance chair)
Mini-symposium committee:
Erik D'Hollander, Ghent University
Abdellah Touhafi, Brussels University
Program committee:
Ivan Beretta, University of Westminster, UK
Erik D'Hollander, Ghent University, Belgium, (chair)
Frank Hannig, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany
Mike Hutton, Altera, USA
Tsutomu Maruyama, University of Tsukuba, Japan
Christian Pilato, Columbia University, USA
Dionisios Pnevmatikatos, Technical University of Crete, Greece
Viktor Prasanna, University of Southern California, USA
Abdellah Touhafi, Vrije Universiteit Brussel, Belgium, (co-chair)
Sotirios G. Ziavras, New Jersey Institute of Technology, USA
IMPORTANT DATES:
- Submission deadline: 10 June 2017
- Notification of acceptance: 20 July 2017
- Final papers due: 20 August 2017
CONTACT
e-Mail: parafpga@elis.ugent.be
Website: http://parafpga.elis.ugent.be/
SCOPE
Parallel computing with Field Programmable Gate Arrays (ParaFPGA) brings together research on tools, programming environments and applications using FPGAs for high performance computing. High performance computing requires new avenues and creative solutions to alleviate the power and frequency limitations of today's processors. Accelerators are becoming the mainstream approach for delegating compute intensive tasks to appropriate hardware. The diversity of architectures and high-level synthesis designs are harnessed with common languages such as OpenCL combined with dedicated programming and synthesis environments.
Researchers and practitioners are invited to submit original contributions on the methodology and use of parallel computing with FPGAs. Papers are solicited in areas including but not limited to:
- performance analysis of high-level synthesis
- design space exploration using HLS
- applications of parallel techniques with FPGAs e.g. in big data, deep learning, biology and finance
- high-level synthesis debugging
- domain specific synthesis languages
- optimizing memory locality and data paths
- partial reconfiguration and optimal ip-core (re)use
- managing a run-time library of ip-cores
- use of hybrid CPU/GPU/FPGA systems e.g. in real-time video or automotive systems
- modeling and simulation of FPGA architectures and applications
PAPERS
Authors are invited to submit a full paper of maximum 10 pages or an extended abstract of minimal 4 pages. The approved contributions will be presented at the conference and the accepted full papers are published in the ParCo proceedings.
Details regarding the format, presentation and paper submission are given on the author guidelines page.
Deadline for the submission is 10 June 2017
COMMITTEES
Steering committee:
Gerhard R. Joubert (Conference chair)
Sanzio Bassini (Organizing committee chair)
Frans Peters (Finance chair)
Mini-symposium committee:
Erik D'Hollander, Ghent University
Abdellah Touhafi, Brussels University
Program committee:
Ivan Beretta, University of Westminster, UK
Erik D'Hollander, Ghent University, Belgium, (chair)
Frank Hannig, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany
Mike Hutton, Altera, USA
Tsutomu Maruyama, University of Tsukuba, Japan
Christian Pilato, Columbia University, USA
Dionisios Pnevmatikatos, Technical University of Crete, Greece
Viktor Prasanna, University of Southern California, USA
Abdellah Touhafi, Vrije Universiteit Brussel, Belgium, (co-chair)
Sotirios G. Ziavras, New Jersey Institute of Technology, USA
IMPORTANT DATES:
- Submission deadline: 10 June 2017
- Notification of acceptance: 20 July 2017
- Final papers due: 20 August 2017
CONTACT
e-Mail: parafpga@elis.ugent.be
Website: http://parafpga.elis.ugent.be/
Journal Promotion
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